Low power CMOS adaptive electronic central pattern generator design
Young Jun Lee
Jihyun Lee
Yong-Bin Kim
Ayers, J.
Dept. of Comput. Eng., Northeastern Univ., Boston, MA;
This paper appears in: Circuits and Systems, 2005. 48th Midwest Symposium on
Publication Date: 7-10 Aug. 2005
On page(s): 1350-1353 Vol. 2
Location: Covington, KY,
ISBN: 0-7803-9197-7
INSPEC Accession Number: 8967470
Digital Object Identifier: 10.1109/MWSCAS.2005.1594360
Current Version Published: 2006-02-21
Abstract
In this paper, low power VLSI implementation of adaptive analog controller for autonomous robot is presented using standard CMOS process with 2V supply voltage. Electronic neuron and synapse circuit are developed based on Hindmarsh-Rose neuron model and first order synapse model. In order to achieve low power consumption, CMOS subthreshold circuit techniques are used. The power consumption is 4.8 mW and die size is 2mm by 2mm. Simulation results demonstrate that the proposed design is viable for adaptive analog controller for autonomous robots
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