The implementation of a 2-core, multi-threaded itanium family processor
Naffziger, S.
Stackhouse, B.
Grutkowski, T.
Josephson, D.
Desai, J.
Alon, E.
Horowitz, M.
Intel Corp., Fort Collins, CO, USA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Jan. 2006
Volume: 41,
Issue: 1
On page(s): 197- 209
ISSN: 0018-9200
INSPEC Accession Number: 8710515
Digital Object Identifier: 10.1109/JSSC.2005.859894
Current Version Published: 2005-12-27
Abstract
The design of the high end server processor code named Montecito incorporated several ambitious goals requiring innovation. The most obvious being the incorporation of two legacy cores on-die and at the same time reducing power by 23%. This is an effective 325% increase in MIPS per watt which necessitated a holistic focus on power reduction and management. The next challenge in the implementation was to ensure robust and high frequency circuit operation in the 90-nm process generation which brings with it higher leakage and greater variability. Achieving this goal required new methodologies for design, a greatly improved and tunable clock system and a better understanding of our power grid behavior all of which required new circuits and capabilities. The final aspect of circuit design improvement involved the I/O design for our legacy multi-drop system bus. To properly feed the two high frequency cores with memory bandwidth we needed to ensure frequency headroom in the operation of the bus. This was achieved through several innovations in controllability and tuning of the I/O buffers which are discussed as well.
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
