Maximum likelihood decoding of the partial response signal with analog parallel processing circuits of the CNN
Hongrak Son
Hyongsuk Kim
Joungmi Choi
Jeong Won Lee
Chua, L.O.
Commun. & Network Lab., Samsung Adv. Inst. of Technol., Yongin, South Korea;
Abstract
The partial response maximum likelihood (PRML) decoder is designed with the analog parallel processing circuits of the CNN. The PR technology is incorporated with the multi-level coding and normally used for the high density magnetic storage device or DVD. The technology combined with the optimization is called PRML and used for error correction of the storage device. Being required lots of computation in the PRML, the parallel processing structure with the CNN's massive connections is able to be an efficient solution. In this study, a decoder for the PR signal called PR(1 2 2 1) is designed with the analog parallel circuits of the CNN. The circuits are connected circularly, which enables to decode the symbols continually. On-trellis circuit decoding enables faster decoding. The circuit simulations show that the power consumption of the proposed one is 1/3 and its silicon area is 1/2 of the digital Viterbi decoder to achieve the similar error correction performance.
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