Abstract
A parallel implementation of the ISO 8802-2.2 Logical Link Control
protocol on a multiprocessor-based communication adapter is described.
Detailed measurements allow the authors to construct and parameterize a
model of the implementation. The model shows how pipelining of different
protocol functions is possible and what performance gain can be expected
when running the implementation on different processor configurations.
The performance of the parallel implementation is more than 16000
information protocol data units per second, commensurate with emerging
high-speed networks operating in the 100 Mb/s range
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