Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications
Bornoosh, B.
Afzali-Kusha, A.
Dehghani, R.
Mehrara, M.
Atarodi, S.M.
Nourani, M.
Dept. of Electr. & Comput. Eng., Univ. of Tehran, Iran;
This paper appears in: Circuits, Devices and Systems, IEE Proceedings -
Publication Date: 7 Oct. 2005
Volume: 152,
Issue: 5
On page(s): 471- 477
ISSN: 1350-2409
INSPEC Accession Number: 8606762
Digital Object Identifier: 10.1049/ip-cds:20045179
Current Version Published: 2005-10-24
Abstract
A reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The high-performance modulator, which consists of two sub-blocks, has a single-bit output making it best for this sort of application. A good shaping of quantisation noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this modulator is considerably less than that in previously reported leading to lower power and area consumption and a higher operating frequency. The field programmable gate array (FPGA) implementation of the whole system shows an SNR of at least 94 dB and an operating input range of 0.7 of the full scale (0.7 FS) with an oversampling ratio of 167. The post-layout simulation of the digital circuit using 0.25 μm CMOS technology predicts a maximum operating frequency of over 60 MHz at a supply voltage of 1.5 V.
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
