A general simulator for VLSI lithography and etching processes: Part II—Application to deposition and etching
Oldham, W.G.
Neureuther, A.R.
Chiakang Sung
Reynolds, J.L.
Nandgaonkar, S.N.
This paper appears in: Electron Devices, IEEE Transactions on
Publication Date: Aug 1980
Volume: 27,
Issue: 8
On page(s): 1455- 1459
ISSN: 0018-9383
Current Version Published: 2005-08-09
Abstract
The extension of the general process simulator SAMPLE to plasma etching and metallization is described. The etching algorithm is divided into isotropic, anisotropic, and direct milling components and is suitable for modeling wet etching, plasma etching, reactive ion etching, and ion milling. Separate deposition algorithms are used for CVD, sputtering, and planetary deposition. With the extension, it is possible to use a simple keyword repertoire to simulate a sequence of photolithography, etching, and deposition steps to obtain device cross sections at each stage of fabrication.
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