A new low voltage CMOS current controlled oscillator with minimum phase noise

In this paper, we present a design of a current controlled oscillator in a 0.35 /spl mu/m CMOS process. Owing to its high degree of controllability, the second generation current conveyor is used as a basic block for our oscillator. Thus, the first step in our design is to develop an improved version of second generation current conveyors operating at /spl plusmn/1.5 V and presenting a current controlled parasitic resistance at port X. Under a current control of 25 /spl mu/A, a resistance value of 60 /spl Omega/ is obtained corresponding to an improvement of a factor of 10. This improved CCII version was used as a basic building block in the design of a current controlled oscillator covering [15 MHz-150 MHz] frequency range. Phase noise characteristics of the proposed oscillator are investigated. We present then a new methodology of modelling and optimisation of phase noise of current controlled oscillators for CMOS process. This optimization strategy leads to a minimum phase noise acting on device geometries and design sources.