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Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery
Stojanovic, V. Ho, A. Garlepp, B.W. Chen, F. Wei, J. Tsang, G. Alon, E. Kollipara, R.T. Werner, C.W. Zerbe, J.L. Horowitz, M.A.
Rambus Inc., Los Altos, CA, USA;

This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: April 2005
Volume: 40, Issue: 4
On page(s): 1012- 1026
ISSN: 0018-9200
INSPEC Accession Number: 8387235
Digital Object Identifier: 10.1109/JSSC.2004.842863
Current Version Published: 2005-04-25

Abstract
This paper describes an adaptively equalized, dual-mode (PAM2 one-tap DFE/PAM4) 0.13 μm CMOS transceiver chip, and the techniques used to continuously adapt the link. Interestingly, with only minor modification the same hardware needed to implement a PAM4 system can be used to implement a PAM2 loop-unrolled single-tap decision-feedback equalization (DFE) receiver. Adaptive equalization using data-based update filtering allows continuous updates while minimizing the required sampler front-end hardware and significantly reduces the cost of implementation in multi-level signaling schemes. To allow the transmitter to adapt to the channel, the link uses common-mode signaling to create a back-channel communication path over the existing pair of wires. The design uses a three-level return-to- signaling scheme which allows the receiver to simultaneously extract voltage and timing references and minimize the required receiver hardware. The measured results indicate that this back-channel achieves reliable communication without noticeable impact on the forward link for back-channel data rates of up to 16 Mb/s and swings of 20-100 mV.

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