FPGA implementation of an integer MIPS processor in Handel-C and its application to human face detection
Ramdas, T.
Li-minn Ang
Egan, G.
Sch. of Eng., Monash Univ., Malaysia;
This paper appears in: TENCON 2004. 2004 IEEE Region 10 Conference
Publication Date: 21-24 Nov. 2004
Volume: A,
On page(s): 36- 39 Vol. 1
ISBN: 0-7803-8560-8
INSPEC Accession Number: 8495495
Digital Object Identifier: 10.1109/TENCON.2004.1414350
Current Version Published: 2005-05-23
Abstract
We present an FPGA implementation of an integer-based MIPS processor using the Handel-C hardware design language (HDL). The processor is implemented on the RC200 development board from Celoxica. The processor implementation is modified from the standard MIPS architecture to take into account the limitations and features of the board. A face detection system is implemented with the processor to show its application towards real-time image processing.
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