Implementation of PBS/spl I.bar/LMS algorithm for adaptive filters on FPGA

In this paper the result of implementing the PBS/spl I.bar/LMS algorithm is reported. Transversal adaptive filters for digital signal processing have traditionally been implemented onto DSP processors due to their ability to perform fast floating-point arithmetic operations. Motorola implemented an adaptive filter on ASICS technology (DSP56300). However, with its growing die size as well as incorporating the embedded digital signal processing blocks, the FPGA devices have become a serious contender in the signal processing market. In this paper an adaptive filter is implemented on 2V1500bg575 (Virtex-II family) and on EPIS25F1020C (Stratix family) FPGA from XiIinx and Altera companies. A comparison with this implementation shows a speed about 10:1 with respect to Motorola ASICS is achieved.