Razor: circuit-level correction of timing errors for low-power operation
Ernst, D.
Das, S.
Lee, S.
Blaauw, D.
Austin, T.
Mudge, T.
Nam Sung Kim
Flautner, K.
This paper appears in: Micro, IEEE
Publication Date: Nov.-Dec. 2004
Volume: 24,
Issue: 6
On page(s): 10-20
ISSN: 0272-1732
INSPEC Accession Number: 8293728
Digital Object Identifier: 10.1109/MM.2004.85
Current Version Published: 2005-01-31
Abstract
Dynamic voltage scaling is one of the more effective and widely used methods for power-aware computing. We present a DVS approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage margins
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