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Efficient statistical timing analysis through error budgeting
Khandelwal, V.   Davoodi, A.   Srivastava, A.  
Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA;

This paper appears in: Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
Publication Date: 7-11 Nov. 2004
On page(s): 473- 477
ISSN: 1092-3152
ISBN: 0-7803-8702-3
INSPEC Accession Number: 8246377
Current Version Published: 2005-01-31

Abstract
We propose a technique for optimizing the runtime in statistical timing analysis. Given a global acceptable error budget at the primary output which signifies the difference in the area of the accurate and approximate timing CDFs, we propose a formulation of budgeting this global error across all nodes in the circuit. This node error budget is used to simplify the computation of arrival time CDFs at each node using approximations. This simplification reduces the runtime of statistical timing analysis. We investigate two ways of exploiting this node error budget, firstly through piecewise linear approximation (see ibid., A. Devgan and C. Kashyap, 2003) and secondly though hierarchical quadratic approximation. Experimental results on ISCAS/MCNC benchmarks show that our approach is at most 3 times faster than accurate statistical timing analysis and had a very small error. We also found quadratic piecewise approximation to be more accurate than linear approximation but at lesser gains in runtime.

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