Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS
Mai, K.
Ho, R.
Alon, E.
Liu, D.
Younggon Kim
Patil, D.
Horowitz, M.A.
Center for Integrated Syst., Stanford, CA, USA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Jan. 2005
Volume: 40,
Issue: 1
On page(s): 261- 275
ISSN: 0018-9200
INSPEC Accession Number: 8258396
Digital Object Identifier: 10.1109/JSSC.2004.837992
Current Version Published: 2005-01-03
Abstract
This paper presents the architecture and circuit techniques for a reconfigurable SRAM building block. The memory block can emulate many memory structures including a cache tag or data array, a FIFO, and a simple scratchpad memory. We choose the block size based on the optimal partition size for large SRAM structures, use self-resetting and replica timing circuit techniques, and add flexible status bits and a few hardwired functional blocks to support reconfigurability. A 16-kb prototype design fabricated in a 0.18 μm technology cycles at 1.1 GHz at the nominal 1.8 V supply and room temperature. The additional logic used for reconfigurability consumes 32 % of the area and 23 % of the power of the memory block. We project that these overhead percentages would fall below 15% and 10%, respectively, for a 64-kb memory.
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