Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization
Runzi Chang
Yu Cao
Spanos, C.J.
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA;
This paper appears in: Electron Devices, IEEE Transactions on
Publication Date: Oct. 2004
Volume: 51,
Issue: 10
On page(s): 1577- 1583
ISSN: 0018-9383
INSPEC Accession Number: 8155298
Digital Object Identifier: 10.1109/TED.2004.834898
Current Version Published: 2004-09-27
Abstract
A dishing model is developed to investigate the electrical effects of metal dishing in the damascene process, based on experimental data and physical analysis. A metric for dishing, the dishing radius, has been defined. A study utilizing this model shows that the impact of dishing on performance can be mitigated at both the process and design stages. More specifically, process improvement is most effective when the dishing radius is less than 50 μm. During design, dishing effects can be suppressed by uniformly splitting a wide line into several narrower lines; the most beneficial number of line-splitting is between two and four from both efficiency and performance considerations.
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