Welcome to IEEE Xplore 2.0: Architecture and circuit techniques for a reconfigurable memory block

Cart | Sitemap | Help

Abstract


	BROWSE	SEARCH	IEEE XPLORE GUIDE	SUPPORT

View TOC

Architecture and circuit techniques for a reconfigurable memory block
Mai, K. Ho, R. Alon, E. Dean, L. Younggon Kim Dinesh, P. Horowitz, M.
Stanford Univ., CA, USA;

This paper appears in: Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Publication Date: 15-19 Feb. 2004
On page(s): 500- 542 Vol.1
ISSN: 0193-6530
ISBN: 0-7803-8267-6
INSPEC Accession Number: 8056965
Digital Object Identifier: 10.1109/ISSCC.2004.1332813
Current Version Published: 2004-09-13

Abstract
A 2 kB reconfigurable SRAM block, using self-timed, pulse-mode circuits capable of emulating a portion of a cache or a streaming FIFO is realized in a 1.8 V 0.18 μm CMOS process and operates at 1.1 GHz (10F04 cycle). The additional logic needed for reconfigurability consumes 26% of the total power and 32% of the total area.

Index Terms
Available to subscribers and IEEE members.

References
Available to subscribers and IEEE members.

Citing Documents
Available to subscribers and IEEE members.

You are not logged in.

Guests may access Abstract records free of charge.