Performance models for evaluation and automatic tuning of symmetric sparse matrix-vector multiply
Lee, B.C.
Vuduc, R.W.
Demmel, J.W.
Yelick, K.A.
Div. of Comput. Sci., California Univ., Berkeley, CA, USA;
This paper appears in: Parallel Processing, 2004. ICPP 2004. International Conference on
Publication Date: 15-18 Aug. 2004
On page(s): 169- 176 vol.1
ISSN: 0190-3918
ISBN: 0-7695-2197-5
INSPEC Accession Number: 8289379
Digital Object Identifier: 10.1109/ICPP.2004.1327917
Current Version Published: 2004-08-30
Abstract
We present optimizations for sparse matrix-vector multiply SpMV and its generalization to multiple vectors, SpMM, when the matrix is symmetric: (1) symmetric storage, (2) register blocking, and (3) vector blocking. Combined with register blocking, symmetry saves more than 50% in matrix storage. We also show performance speedups of 2.1× for SpMV and 2.6× for SpMM, when compared to the best nonsymmetric register blocked implementation. We present an approach for the selection of tuning parameters, based on empirical modeling and search that consists of three steps: (1) Off-line benchmark, (2) Runtime search, and (3) Heuristic performance model. This approach generally selects parameters to achieve performance with 85% of that achieved with exhaustive search. We evaluate our implementations with respect to upper bounds on performance. Our model bounds performance by considering only the cost of memory operations and using lower bounds on the number of cache misses. Our optimized codes are within 68% of the upper bounds.
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