Modeling of interfacial sliding and film crawling in back-end structures of microelectronic devices

Interconnect structures at the back-end of microelectronic devices can deform via unusual, scale-sensitive phenomena due to thermo-mechanical loads sustained during processing, or during service as part of a microelectronic package. Although small, these effects can have a pronounced effect on component reliability. Here, we present results of atomic force microscopy (AFM) studies on Cu-low K dielectric (LKD) back-end interconnect structures (BEIS) to demonstrate these effects, which include creep/plasticity of interconnect lines, and diffusionally accommodated sliding at Cu-LKD interfaces. These effects may result in in-plane (IP) changes in Cu line dimensions, cause strain incompatibilities between Cu and LKD in the out-of-plane (OOP) direction, and cause Cu lines to migrate or crawl under far-field shear stresses imposed by the package. A shear-lag based model is utilized to simulate OOP deformation in a Cu-LKD single layer BEIS under thermal cycling conditions associated with back-end processing. A separate model, which simulates IP deformation of Cu interconnects embedded in LKD under thermo-mechanical cycling conditions imposed when the chip is attached to a flip-chip package, is also presented. The models, which incorporate a constitutive interfacial sliding law developed by us previously, help rationalize the experimental AFM observations.