"Software-pipelined" 2-D discrete wavelet transform with VLSI hierarchical implementation
Chunhui Zhang
Yun Long
Seong Yong Oum
Kurdahi, F.
Dept. of Electr. & Comput. Eng.,, California Univ., Irvine, CA, USA;
Abstract
Numerous VLSI architectures for 2-D discrete wavelet transform (DWT) have been introduced. While most of the designs displayed good performance, few of them discussed thoroughly how to sustain such high throughput computing. The reasons behind this are the design complexity, costs of peripherals, and performance degradation caused by overhead. In this paper, we expose the performance gap between the computing core and the entire system, distinguishing them by quantitative approach with metrics-peak performance and mean-time performance. To balance the gap, a "software pipelined" formula for lifting-based DWT kernel, a novel enhanced DMA engine named iDMA, and a complete design of 2-D DWT using hierarchical pipelining method are proposed. Finally, the architecture has been implemented in Xilinx virtex-II xc2v500-5. We use Daubechies (9, 7) filter, the default lossy filter of JPEG2000, for illustration whereas it is a general method for other filters. The post-PAR operation frequency is 98 MHz and the peak performance is 1 sample/cycle. Notably, the mean-time performance parameterized by image size and decomposition level achieves closely to peak performance.
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