The Stanford Dash multiprocessor
Lenoski, D.
Laudon, J.
Gharachorloo, K.
Weber, W.-D.
Gupta, A.
Hennessy, J.
Horowitz, M.
Lam, M.S.
Stanford Univ., CA;
This paper appears in: Computer
Publication Date: Mar 1992
Volume: 25,
Issue: 3
On page(s): 63-79
ISSN: 0018-9162
References Cited: 13
CODEN: CPTRB4
INSPEC Accession Number: 4161426
Digital Object Identifier: 10.1109/2.121510
Current Version Published: 2002-08-06
Abstract
The overall goals and major features of the directory architecture
for shared memory (Dash) are presented. The fundamental premise behind
the architecture is that it is possible to build a scalable
high-performance machine with a single address space and coherent
caches. The Dash architecture is scalable in that it achieves linear or
near-linear performance growth as the number of processors increases
from a few to a few thousand. This performance results from distributing
the memory among processing nodes and using a network with scalable
bandwidth to connect the nodes. The architecture allows shared data to
be cached, significantly reducing the latency of memory accesses and
yielding higher processor utilization and higher overall performance. A
distributed directory-based protocol that provides cache coherence
without compromising scalability is discussed in detail. The Dash
prototype machine and the corresponding software support are described
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