Construction of irregular LDPC codes with low error floors
Tao Tian
Jones, C.
Villasenor, J.D.
Wesel, R.D.
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA;
This paper appears in: Communications, 2003. ICC '03. IEEE International Conference on
Publication Date: 11-15 May 2003
Volume: 5,
On page(s): 3125- 3129 vol.5
ISBN: 0-7803-7802-4
INSPEC Accession Number: 7906140
Digital Object Identifier: 10.1109/ICC.2003.1203996
Current Version Published: 2003-06-11
Abstract
This work explains the relationship between cycles, stopping sets, and dependent columns of the parity check matrix of low-density parity-check (LDPC) codes. Furthermore, it discusses how these structures limit LDPC code performance under belief propagation decoding. A new metric called extrinsic message degree (EMD) measures cycle connectivity in bipartite graph. Using an easily computed estimate of EMD, we propose a Viterbi-like algorithm that selectively avoids cycles and increases stopping set size. This algorithm yields codes with error floors that are orders of magnitude below those of girth-conditional codes.
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