Abstract
This paper describes systolic realizations of FIR and IIR digital filters with sample rates much higher than the speed of a single "arithmetic unit" or "processing element." The architecture trades increased throughput for increased latency. For IIR filters, the technique is based on block-state filter descriptions in which the state update matrix is converted to triangular or "quasi-triangular" form via a unitary or orthogonal similarity transformation. The effect of this transformation on the roundoff noise is examined in the Appendix. The latency, complexity, and suitability to VLSI implementations are considered, as well as an attractive application to interpolation and decimation.
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