Low-power CMOS digital design
Chandrakasan, A.P.
Sheng, S.
Brodersen, R.W.
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Apr 1992
Volume: 27,
Issue: 4
On page(s): 473-484
ISSN: 0018-9200
References Cited: 28
CODEN: IJSCBC
INSPEC Accession Number: 4165927
Digital Object Identifier: 10.1109/4.126534
Current Version Published: 2002-08-06
Abstract
Motivated by emerging battery-operated applications that demand
intensive computation in portable environments, techniques are
investigated which reduce power consumption in CMOS digital circuits
while maintaining computational throughput. Techniques for low-power
operation are shown which use the lowest possible supply voltage coupled
with architectural, logic style, circuit, and technology optimizations.
An architecturally based scaling strategy is presented which indicates
that the optimum voltage is much lower than that determined by other
scaling considerations. This optimum is achieved by trading increased
silicon area for reduced power consumption
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