Design challenges of technology scaling
Borkar, S.
Intel Corp.;
This paper appears in: Micro, IEEE
Publication Date: Jul-Aug 1999
Volume: 19,
Issue: 4
On page(s): 23-29
ISSN: 0272-1732
References Cited: 3
CODEN: IEMIDZ
INSPEC Accession Number: 6339844
Digital Object Identifier: 10.1109/40.782564
Current Version Published: 2002-08-06
Abstract
Scaling advanced CMOS technology to the next generation improves
performance, increases transistor density, and reduces power
consumption. Technology scaling typically has three main goals: 1)
reduce gate delay by 30%, resulting in an increase in operating
frequency of about 43%; 2) double transistor density; and 3) reduce
energy per transition by about 65%, saving 50% of power (at a 43%
increase in frequency). These are not ad hoc goals; rather, they follow
scaling theory. This article looks closely at past trends in technology
scaling and how well microprocessor technology and products have met
these goals. It also projects the challenges that lie ahead if these
trends continue. This analysis uses data from various Intel
microprocessors; however, this study is equally applicable to other
types of logic designs. Is process technology meeting the goals
predicted by scaling theory? An analysis of microprocessor performance,
transistor density, and power trends through successive technology
generations helps identify potential limiters of scaling, performance,
and integration
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