A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI
Tierno, J.A.
Rylyakov, A.V.
Friedman, D.J.
IBM Thomas J. Watson Res. Center, Yorktown Heights;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Jan. 2008
Volume: 43,
Issue: 1
On page(s): 42-51
Location: Lille, France,
ISSN: 0018-9200
INSPEC Accession Number: 9757298
Digital Object Identifier: 10.1109/JSSC.2007.910966
Current Version Published: 2008-01-28
Abstract
An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral-differential (PID) loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL lock range is 500 MHz to 8 GHz at 1.3 V and 25degC, and 90 MHz to 1.2 GHz at 0.5 V and 100degC. The IC dissipates 8 mW/GHz at 1.2 V and 1.6 mW/GHz at 0.5 V. The synthesized 4 GHz clock has a period jitter of 0.7 ps rms, and long term jitter of 6 ps rms. The phase noise under nominal operating conditions is 112 dBc/Hz measured at a 10 MHz offset from a 4 GHz center frequency. The total circuit area is 200 mum 150 mum.
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