Flexibility of interconnection structures for field-programmablegate arrays
Rose, J.
Brown, S.
Dept. of Electr. Eng., Toronto Univ., Ont.;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Mar 1991
Volume: 26,
Issue: 3
On page(s): 277-282
Meeting Date: 05/13/1990 - 05/16/1990
Location: Boston, MA, USA
ISSN: 0018-9200
References Cited: 18
CODEN: IJSCBC
INSPEC Accession Number: 3911421
Digital Object Identifier: 10.1109/4.75006
Current Version Published: 2002-08-06
Abstract
The relationship between the routability of a field-programmable
gate array (FPGA) and the flexibility of its interconnection structures
is examined. The flexibility of an FPGA is determined by the number and
distribution of switches used in the interconnection. While good
routability can be obtained with a high flexibility, a large number of
switches will result in poor performance and logical density because
each switch has significant delay and area. The minimum number of
switches required to achieve good routability is determined by
implementing several industrial circuits in a variety of interconnection
architectures. These experiments indicate that high flexibility is
essential for the connection block that joins the logic blocks to the
routing channel, but a relative low flexibility is sufficient for switch
blocks at the junction of horizontal and vertical channels. Furthermore,
it is necessary to use only a few more routing tracks than the absolute
minimum possible with structures of surprisingly low flexibility
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