How much logic should go in an FPGA logic block
Betz, V.
Rose, J.
Toronto Univ., Ont.;
This paper appears in: Design & Test of Computers, IEEE
Publication Date: Jan-Mar 1998
Volume: 15,
Issue: 1
On page(s): 10-15
ISSN: 0740-7475
References Cited: 8
CODEN: IDTCEC
INSPEC Accession Number: 5852379
Digital Object Identifier: 10.1109/54.655177
Current Version Published: 2002-08-06
Abstract
The logic blocks of most FPGAs contain clusters of lookup tables
and flip-flops yet little is known about good choices for key
parameters. How many lookup tables should a cluster contain, how should
FPGA routing flexibility change as cluster size changes, and how many
inputs should programmable routing provide each cluster?
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