A time-multiplexed FPGA
Trimberger, S.
Carberry, D.
Johnson, A.
Wong, J.
Xilinx Inc., San Jose, CA;
This paper appears in: FPGAs for Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on
Publication Date: 16-18 Apr 1997
On page(s): 22-28
Meeting Date: 04/16/1997 - 04/18/1997
Location: Napa Valley, CA, USA
ISBN: 0-8186-8159-4
References Cited: 7
INSPEC Accession Number: 5731371
Digital Object Identifier: 10.1109/FPGA.1997.624601
Current Version Published: 2002-08-06
Abstract
This paper describes the architecture of a time-multiplexed FPGA.
Eight configurations of the FPGA are stored in on-chip memory. This
inactive on-chip memory is distributed around the chip, and accessible
so that the entire configuration of the FPGA can be changed in a single
cycle of the memory. The entire configuration of the FPGA can be loaded
from this on-chip memory in 30 ns. Inactive memory is accessible as
block RAM for applications. The FPGA is based on the Xilinx XC4000E
FPGA, and includes extensions for dealing with state saving and
forwarding and for increased routing demand due to time-multiplexing the
hardware
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