Architecture of field-programmable gate arrays: the effect of logicblock functionality on area efficiency
Rose, J.
Francis, R.J.
Lewis, D.
Chow, P.
Dept. of Electr. Eng., Toronto Univ., Ont.;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Oct 1990
Volume: 25,
Issue: 5
On page(s): 1217-1225
ISSN: 0018-9200
References Cited: 20
CODEN: IJSCBC
INSPEC Accession Number: 3814258
Digital Object Identifier: 10.1109/4.62145
Current Version Published: 2002-08-06
Abstract
The relationship between the functionality of a field-programmable
gate array (FPGA) logic block and the area required to implement digital
circuits using that logic block is examined. The investigation is done
experimentally by implementing a set of industrial circuits as FPGAs
using CAD (computer-aided design) tools for technology mapping,
placement, and routing. A range of programming technologies (the method
of FPGA customization) is explored using a simple model of the
interconnection and logic block area. The experiments are based on logic
blocks that use lookup tables for implementing combinational logic.
Results indicate that the best number of inputs to use (a measure of the
block's functionality) is between three and four, and that a D
flip-flop should be included in the logic block. The results are largely
independent of the programming technology. More generally, it was
observed that the area efficiency of a logic block depends not only on
its functionality but also on the average number of pins connected per
logic block
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