Configurable computing solutions for automatic target recognition
Villasenor, J.
Schoner, B.
Kang-Ngee Chia
Zapata, C.
Hea Joung Kim
Jones, C.
Lansing, S.
Mangione-Smith, B.
Dept. of Electr. Eng., California Univ., Los Angeles, CA;
This paper appears in: FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on
Publication Date: 17-19 Apr 1996
On page(s): 70-79
Meeting Date: 04/17/1996 - 04/19/1996
Location: Napa Valley, CA, USA
ISBN: 0-8186-7548-9
References Cited: 9
INSPEC Accession Number: 5485131
Digital Object Identifier: 10.1109/FPGA.1996.564749
Current Version Published: 2002-08-06
Abstract
FPGAs can be used to build systems for automatic target
recognition (ATR) that achieve an order of magnitude increase in
performance over systems built using general purpose processors. This
improvement is possible because the bit-level operations that comprise
much of the ATR computational burden map extremely efficiently into
FPGAs, and because the specificity of ATR target templates can be
leveraged via fast reconfiguration. We describe here algorithms, design
tools, and implementation strategies that are being used in a
configurable computing system for ATR
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