CMOS scaling for high performance and low power-the next ten years
Davari, B.
Dennard, R.H.
Shahidi, G.G.
SRDC, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY;
This paper appears in: Proceedings of the IEEE
Publication Date: Apr 1995
Volume: 83,
Issue: 4
On page(s): 595-606
ISSN: 0018-9219
References Cited: 43
CODEN: IEEPAD
INSPEC Accession Number: 4949806
Digital Object Identifier: 10.1109/5.371968
Current Version Published: 2002-08-06
Abstract
A guideline for scaling of CMOS technology for logic applications
such as microprocessors is presented covering the next ten years,
assuming that the lithography and base process development driven by
DRAM continues on the same three-year cycle as in the past. This paper
emphasizes the importance of optimizing the choice of power-supply
voltage. Two CMOS device and voltage scaling scenarios are described.
One optimized for highest speed and the other trading off speed
improvement for much lower power. It is shown that the low power
scenario is quite close to the original constant electric-field scaling
theory. CMOS technologies ranging from 0.25 μm channel length at 2.5
V down to sub-0.1 μm at 1 V are presented and power density is
compared for the two scenarios. Scaling of the threshold voltage along
with the power supply voltage will lead to a substantial rise in standby
power compared to active power and some tradeoffs of performance and/or
changes in design methods must be made. Key technology elements and
their impact on scaling are discussed. It is shown that a speed
improvement of about 7× and over two orders of magnitude
improvement in power-delay product (mW/MIPS) are expected by scaling of
bulk CMOS down to the sub-0.1 μm regime as compared with today's high
performance 0.6 μm devices at 5 V. However, the power density rises
by a factor of 4× for the high-speed scenario. The status of the
silicon-on-insulator (SOI) approach to scaled CMOS is also reviewed,
showing the potential for about 3× savings in power compared to
the bulk case at the same speed
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