Abstract
This paper evaluates an architecture that implements a
hierarchical routing structure for FPGAs, called a hierarchical FPGA
(HFPGA). A set of new tools has been used to place and route several
circuits on this architecture, with the goal of comparing the cost of
HFPGAs to conventional symmetrical FPGAs. The results show that HFPGAs
can implement circuits with fewer routing switches, and fewer switches
in total, compared to symmetrical FGPAs, although they have the
potential disadvantage that they may require more logic blocks due to
coarser granularity
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