Limits to binary logic switch scaling - a gedanken model
Zhirnov, V.V.
Cavin, R.K., III
Hutchby, J.A.
Bourianoff, G.I.
Semicond. Res. Corp., Res. Triangle Park, NC, USA;
This paper appears in: Proceedings of the IEEE
Publication Date: Nov 2003
Volume: 91,
Issue: 11
On page(s): 1934- 1939
ISSN: 0018-9219
INSPEC Accession Number: 7785293
Digital Object Identifier: 10.1109/JPROC.2003.818324
Current Version Published: 2004-11-08
Abstract
In this paper we consider device scaling and speed limitations on irreversible von Neumann computing that are derived from the requirement of "least energy computation." We consider computational systems whose material realizations utilize electrons and energy barriers to represent and manipulate their binary representations of state.
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