The effect of logic block architecture on FPGA performance
Singh, S.
Rose, J.
Chow, P.
Lewis, D.
Dept. of Electr. Eng., Toronto Univ., Ont.;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Mar 1992
Volume: 27,
Issue: 3
On page(s): 281-287
ISSN: 0018-9200
References Cited: 29
CODEN: IJSCBC
INSPEC Accession Number: 4138957
Digital Object Identifier: 10.1109/4.121549
Current Version Published: 2002-08-06
Abstract
This authors explore the effect of logic block architecture on the
speed of a field-programmable gate array (FPGA). Four classes of logic
block architecture are investigated: NAND gates, multiplexer
configurations, lookup tables, and wide-input AND-OR gates. An
experimental approach is taken, in which each of a set of benchmark
logic circuits is synthesized into FPGAs that use different logic
blocks. The speed of the resulting FPGA implementations using each logic
block is measured. While the results depend on the delay of the
programmable routing, experiments indicate that five- and six-input
lookup tables and certain multiplexer configurations produce the lowest
total delay over realistic values of routing delay. The fine grain
blocks, such as the two-input NAND gate, exhibit poor performance
because these gates require many levels of logic block to implement the
circuits and hence require a large routing delay
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