Abstract
Two-dimenslonal stochastic models for Interconnections in master slice LSI are described. Several limit theorems are derived for estimating the wiring area on large chips in terms of average wire lengthbar{R}, average number of wires emanating from each logic blocklambda, and wire trajectory parameters. The expected value of the maximum number of tracks per channel on anN times Nchip is shown to be less thanO(ln N)as long asbar{R}does not grow faster thanO(ln N). Ifbar{R} > O(ln N), then the expected maximum number of tracks isO(bar{R}). Simple bounds on the expected wiring area are given and numerical results compared to the earlier work by Helier et al.
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