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Power Electronic Converters for Microgrids

Cover Image Copyright Year: 2014
Author(s): Suleiman M. Sharkh; Mohammad A. Abu-Sara; Georgios I. Orfanoudakis; Babar Hussain
Publisher: Wiley-IEEE Press
Content Type : Books & eBooks
Topics: Components, Circuits, Devices & Systems ;  Engineered Materials, Dielectrics & Plasmas ;  Power, Energy, & Industry Applications
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      Frontmatter

      Copyright Year: 2014

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      The prelims comprise:
      Half-Title Page
      Title Page
      Copyright Page
      Table of Contents
      About the Authors
      Preface
      Acknowledgments View full abstract»

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      Introduction

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      This chapter presents a review of the state of the art of power electric converters used in microgrids. It focuses primarily on grid connected converters. Different topologies and control and modulation strategies for these specific converters are critically reviewed. Moreover, future challenges in respect of these converters are identified along with their potential solutions. View full abstract»

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      Converter Topologies

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      This Chapters covers the structure, modulation and modelling in MATLAB-Simulink of the the conventional 2 level (2L), and the three level (3L) neutral point clamped (NPC) and cascaded H-bridge (CHB) converter topologies. View full abstract»

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      DC-Link Capacitor Current and Sizing in NPC and CHB Inverters

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      DC-link capacitor sizing is a critical aspect of inverter design. This chapter investigates capacitor sizing for three-level Neutral-Point-Clamped and Cascaded H-Bridge inverters, based on an analysis of dc-link capacitor current. Methods used to derive expressions for the rms value and harmonic spectrum of the capacitor current in two-level inverters, are extended to the three-level inverters. A new numerical approach is also proposed for calculating the capacitor rms current and voltage ripple. MATLAB code is given for the proposed approach, which can be easily adapted to different modulation strategies. Capacitor sizing parameters derived according to this approach are presented for a number of common modulation strategies and are used to compare the requirements of the examined three-level topologies. Results are validated by simulations using MATLAB-Simulink. View full abstract»

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      Loss Comparison of Two- and Three-Level Inverter Topologies

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      This chapter investigates semiconductor and dc link capacitor losses in two two-level and two three-level voltage source inverters. The components of the four inverters are selected to have appropriate voltage and current ratings. Analytical expressions for semiconductor losses are reviewed and expressions for DC link capacitor losses are derived for all topologies. Three-level inverters are found to have lower semiconductor losses, but higher DC-link capacitor losses. Overall, the three-level Neutral-Point-Clamped inverter proved to be the most efficient topology. View full abstract»

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      Minimization of Low-Frequency Neutral-Point Voltage Oscillations in NPC Converters

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      This chapter investigates the problem of low-frequency voltage oscillations that appear at the Neutral Point (NP) of a three-level Neutral-Point-Clamped (NPC) converter. Starting with a detailed analysis of their origin, the chapter derives the minimum amplitude of these oscillations that can be achieved by Nearest-Vector (NV) modulation strategies. It then proves that the criterion of the direction of dc-link capacitor imbalance, which is commonly adopted by NV strategies for performing the task of capacitor balancing, poses a barrier in achieving this minimum. A new criterion is proposed instead, together with an algorithm that incorporates it into existing NV strategies. For the case of NPC inverters operating as grid connected inverters, the resulting reduction in the amplitude of NP voltage oscillations ranges from 30 to 50%. The approach has the advantage of avoiding the significant increment in switching losses and output voltage harmonic distortion, caused by other methods. Simulations in MATLAB-Simulink are used to illustrate its operation and verify that it offers the claimed benefit. View full abstract»

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      Digital Control of a Three-Phase Two-Level Grid-Connected Inverter

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      This chapter presents the design and practical implementation of a digital current controller for a three-phase 2 level voltage source PWM inverter connected to the grid via an LCL filter. A two feedback loops control system is proposed, with an outer grid current loop and an inner filter capacitor current loop. The controller also incorporates a grid voltage feedforward loop to compensate for the effect of the utility voltage disturbance. The chapter also discusses the effect of sampling and computational time delay both on system stability and current quality. The time delay is shown to reduce the stability of the inner loop. However, it is also shown that it is better, from the point of view of output current THD quality, to increase the inner loop time delay to a full one sampling period, so that the mains frequency envelope (nearly ripple free) current component is sampled at the peaks and troughs of the PWM, away from the switching instances (and associated noise) of the transistors. To ensure system stability, a capacitor current observer is proposed to compensate for the computational time delay. The design of the capacitor current observer and the controller are discussed. Simulation and practical results are presented to validate the design. View full abstract»

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      Design and Control of a Grid-Connected Interleaved Inverter

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      This chapter is concerned with the design and control of a three-phase voltage source grid-connected interleaved inverter. This topology enables low current high switching frequency devices to be used. The high switching frequency, together with the ripple cancellation feature of this topology, reduces the size of the output filter and the inverter considerably compared to an equivalent classical 2-level voltage source inverter with an LCL output filter using lower switching frequency high current devices. Due to its higher switching frequency and low filter component values, the interleaved inverter also has a much higher bandwidth than the classical inverter, which improves grid voltage harmonics disturbance rejection and increases the speed of response of the inverter and its capability to ride through grid disturbance (e.g. voltage sags and swells). The chapter discusses the selection of the number of channels and the filter component values of the interleaved inverter. The design of the digital control system is then discussed in detail. Simulation and practical results are presented to validate the design and demonstrate its capabilities. View full abstract»

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      Repetitive Current Control of an Interleaved Grid-Connected Inverter

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      Repetitive control can be effective at improving current quality when used with grid-connected inverters. Mathematically, a repetitive controller is equivalent to a parallel combination of resonant controllers with high gain at the fundamental frequency and its harmonics, and accordingly good disturbance rejection can be achieved at these frequencies. To ensure stability, a low-pass filter needs to be incorporated within the repetitive controller to attenuate the high frequency resonant peaks of the controller gain (above the system's cross-over frequency), without significantly affecting the low frequency resonant peaks corresponding to significant grid harmonics that need to be rejected. The chapter therefore argues that it is desirable that the system and the inverter's output filter should have a high bandwidth - higher than the most significant grid harmonics - which may be counter intuitive. The high bandwidth requirement dictates a high PWM switching frequency, which becomes challenging in high power systems as the maximum achievable switching frequency of power electronic devices reduces as their power rating increases. This limitation can be overcome in low voltage systems by using an interleaved inverter topology in which the power is shared between several 2-level half-bridge inverter legs connected in parallel. In addition to using low power devices capable of high switching frequency, the value of the LC output filter capacitance can be relatively very small thanks to the ripple cancellation feature of the interleaved inverter. Both of these features mean that the bandwidth of an interleaved inverter can be much higher than that achievable using a classical 2-level inverter with an LCL output filter. The paper discusses the design and practical implementation of a repetitive controller for an interleaved inverter with 6 half-bridge legs per phase. Simulat ion and experimental results are also presented to demonstrate the effectiveness of the proposed controller in improving the THD of the output current of the inverter. View full abstract»

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      Line Interactive UPS

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      Line interactive Uninterruptable Power Supply (UPS) systems are good candidates for providing energy storage within a microgrid to help improve its reliability, economy and efficiency. In grid-connected mode, power can be imported from the grid by the UPS to charge its battery; power can also be exported when required, e.g., when the tariffs are advantageous. In stand-alone mode, the UPS supplies local distributed loads in parallel with other sources. A complete line interactive UPS and its control system are presented and discussed in this chapter. Power flow is controlled using the frequency and voltage drooping technique to ensure seamless transfer between grid-connected and stand-alone parallel modes of operation. The traditional way of measuring active and reactive power, which is based on using a low pass filter, is replaced by a real time integration method which is shown to improve the speed of response of the controller. A virtual impedance is utilized to improve the output current THD in grid-connected mode. When power is imported from the grid, an outer voltage controller that regulates the DC-link voltage sets the active power demand for an inner power flow controller. This facilitates smooth transition between battery charging and discharging modes. This controller is designed with the aid of small signal analysis, which is used to model the dynamics of the inner power flow controller. The drooping coefficients are chosen to limit the energy imported by the USP when re-connecting to the grid and to give good transient response. Experimental results of a microgrid consisting of two 60kW line interactive UPS systems are provided to validate the design. View full abstract»

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      Microgrid Protection

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      An effective introduction of distributed generation (DG) into existing distribution networks (DNs) calls for a review of traditional power system protection concepts and strategies. New issues such as activeness of DNs and bidirectional power flow require new protection solutions. This chapter discusses protection issues and challenges arising from the integration of micogrids and DG into the grid. It presents and critically reviews traditional and state of the art protection strategies. Moreover, some alternate protection strategies are proposed and their merits and demerits are discussed. A typical DN with DG is modelled and simulation results for impact of DG on protection system coordination are presented and discussed here. Some solutions are proposed to cope with these problems. View full abstract»

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      An Adaptive Relaying Scheme for Fuse Saving

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      In some situations, utilities may try to save the fuse of a circuit following temporary faults by de-energizing the line with the fast operation of an upstream recloser before the fuse is damaged. This fuse saving practice is accomplished through proper time coordination between a recloser and a fuse. However, installation of microgrid distributed generation (DG) into distribution networks may affect this coordination due to additional fault current contribution from the distributed resources. This phenomenon of recloser-fuse miscoordination is investigated in this chapter with the help of a typical network that employs fuse saving. Limitations of a recloser equipped with time and instantaneous overcurrent elements in respect of fuse saving in the presence of DG is discussed. An adaptive relaying strategy is proposed to ensure fuse saving in the new scenario even in the worst fault conditions. The simulation results obtained by adaptively changing relay settings in response to changing DG configuration confirm that the settings selected theoretically in accordance with the proposed strategy hold well in operation1. View full abstract»

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      SVM for the NPC Converter-MATLAB-Simulink Models

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      DC-Link Capacitor Current Numerical Calculation

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      Index

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