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Enhanced Phase-Locked Loop Structures for Power and Energy Applications

Cover Image Copyright Year: 2014
Author(s): Masoud Karimi-Ghartema
Publisher: Wiley-IEEE Press
Content Type : Books & eBooks
Topics: Components, Circuits, Devices & Systems ;  Engineered Materials, Dielectrics & Plasmas ;  Power, Energy, & Industry Applications
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      Front Matter

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      The prelims comprise:
      Half-Title Page
      Series Page
      Title Page
      Copyright Page
      Dedicated Page
      Brief Contents
      Table of Contents
      Preface
      Acknowledgments
      Acronyms
      Symbols
      Introduction View full abstract»

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      PLL Structures for Single-Phase Applications

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      PLL Basics and Standard Structure

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      This chapter provides an overview of the standard phase-locked loop (PLL) structure and illustrates that this structure is not suitable for power engineering applications. The chapter explains the control objectives in the PLL system. For a pure sinusoidal signal with no distortion or noise, the error in phase locking is in the order of several degrees when a first order integrating plus a lowpass filter (LPF) is used for the loop filter. Adding more low-pass filtering in the loop can decrease the ripples, but, by the time the ripples are small enough, the transient time of the loop is beyond the admissible range for power system applications. This is why this standard PLL structure has not been of much interest in power engineering. View full abstract»

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      Enhanced Phase-Locked Loop

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      This chapter deals with the basic enhanced phase-locked loop (EPLL) structure. The EPLL enhances the standard PLL by removing its main drawback, which is the presence of double-frequency errors. EPLL achieves this task by means of estimating the amplitude of the input signal and using it within a new loop to remove the error. The EPLL provides an estimate of the input signal magnitude and also provides a filtered version of the input signal. It serves as a core and a building block for numerous developments. The chapter focuses on the derivation, principles of operation, linear model, and design guidelines pertaining to the EPLL. The droop control method (DCM) is widely used to control the operation of synchronous generators (SGs) in a power system. Three scenarios are considered to study the dynamic performance of the EPLL: the step jumps in the input signal variables, amplitude modulations, and phase-angle modulations. View full abstract»

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      EPLL Extensions and Modifications

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      This chapter presents several extensions and modifications to the enhanced phase-locked loop (EPLL). It discusses the estimation and rejection of direct current (DC) component and the estimation/mitigation of harmonics. The chapter deals with the soft start problem, problem of large phase jumps, concept of in-loop filters, and windowing in EPLL. Contrary to prefilter and postfilters, the in-loop filters or window functions have very direct and strong impact on the EPLL stability and can even quickly cause instability if they are not properly designed. A design method based on approximate linear analysis is presented. The EPLL with general filtering is introduced for flexible rejection/ mitigation of various frequency components. The possibility of including a phase shift in the EPLL structure in order to compensate for the phase delay of the general filter is also discussed. This can improve the transient response of the system. View full abstract»

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      Digital Implementation of EPLL

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      This chapter discusses the digital implementation of the enhanced phase-locked loop (EPLL). Its employment as a resonant controller in the context of two practical applications is presented and discussed. This controller has high robustness for digital implementations in applications involving low sampling frequency or applications involving fixed-point word-length limitations at high sampling frequency. Moreover, it offers the frequency adaptivity and phase compensation features. The chapter begins with a discussion on first-order digitization. The linear time invariant (LTI)-EPLL offers high robustness features for digital implementations. The chapter also illustrates some aspects of this robustness by way of numerical examples. It studies the application of the EPLL as a resonant controller with desirable numerical robustness and phase compensation ability. View full abstract»

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      Integrated Synchronization and Control

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      The integrated synchronization and control (ISC) method presented in this chapter resembles an enhanced phase-locked loop (EPLL). The chapter shows that similar analysis and design methods developed for the EPLL are applicable to the ISC as well. The method is discussed in the context of a grid-connected single-phase inverter. A grid-connected converter (GCC) is responsible for (i) DC/AC conversion, (ii) controlling flow of power, and (iii) ensuring satisfactory quality of power. The ISC method works directly on the inverter voltage. The chapter presents a theorem that plays a key role in stability analysis of the ISC system. The ISC method can be improved to reject or mitigate possible current harmonics if they are beyond the admissible limits. The analysis presented here concerns impacts of uncertainties in the filter reactance and the grid voltage magnitude on the steady state accuracy of the ISC method in following external real and reactive commands. View full abstract»

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      PLL Structures for Three-Phase Applications

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      Synchronous Reference Frame PLL

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      The synchronous reference frame phase-locked loop (SRF-PLL) avoids the double-frequency error problem of single-phase standard PLL. It has a relatively simple structure that offers ease of parameter tuning and robust features for digital implementation. This chapter presents an overview of the commonly used three-phase SRF-PLL. The structure, linear analysis, and numerical results are discussed. The representation of the SRF-PLL in the stationary frame shows that the three-phase SRF-PLL does not really need to have three input signals to operate. It can operate if it is supplied by phase-a signal and its orthogonal version that is its 90?? phase shifted version. The chapter explains the correspondence between SRF-PLL and single-phase EPLL. The impact of unbalance, direct current (DC), and harmonics on SRF-PLL is discussed. View full abstract»

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      Three-Phase EPLL-I

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      There are multiple extensions of the enhanced phase-locked loop (EPLL) to three-phase, and they are grouped under the name three-phase EPLL (3EPLL). This chapter presents the first member of this group called the 3EPLL-I. This structure can address direct current (DC) component and harmonics within its loop structure; something that is not possible with the synchronous reference frame (SRF)-PLL. The chapter focuses on the detail derivation, analysis, design, and modifications of the 3EPLL-I. It begins with a discussion on the 3EPLL, and explains the relationship between 3EPLL-I and SRF-PLL. Next, the chapter talks about 3EPLL-I in stationary frame and the mathematical derivation of 3EPLL-I . Numerical simulations show that the responses of the 3EPLL-I and the SRF-PLL are identical. View full abstract»

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      Three-Phase EPLL-II

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      This chapter presents the second member of the three-phase enhanced phase-locked loop (3EPLL) structures. This structure, called the 3EPLL-II, is a direct extension of the 3EPLL-I in order to obviate its major shortcoming with regard to input signal unbalance. The 3EPLL-II inherits all properties of the 3EPLL-I, and in addition to those, it avoids the double-frequency error caused by the negative-sequence component. The 3EPLL-II is comprised of a 3EPLL-I on top and another modified 3EPLL-I on the bottom. The chapter explains the derivation of 3EPLL-II and the modular representation of 3EPLL-II. Representation of the 3EPLL-II in stationary domain is developed and a linear time invariant (LTI) model for the 3EPLL-II is derived for design purposes. The chapter highlights that the performance of the 3EPLL-II is controlled by two gains which makes its design stage very simple. View full abstract»

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      Structural Extensions to 3EPLL-I and 3EPLL-II

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      This chapter presents several extensions to the three-phase enhanced phase-locked loop (EPLL) structures. These extensions are equally applicable to both the 3EPLL-I and the 3EPLL-II. They include estimation of the zero-sequence component, estimation and rejection of direct current (DC) component, and estimation and rejection of harmonics. The 3EPLL structures allow estimation of the direct current (DC) components within the control loop. Since the DC component is estimated within the loop, the error caused by this component is completely removed from the other PLL variables including phase angles, magnitudes, and the frequency. When a 3EPLL structure is added with a DC loop and harmonic units, the number of adjusting parameters goes up. Therefore, the design of parameters needs to be done more carefully in order to ensure desirable performance of the whole system. View full abstract»

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      Three-Phase EPLL-III

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      This chapter deals with the three-phase phase-locked loop (PLL) structure, called the 3EPLL-III, that is structurally different from 3EPLL-I and 3EPLL-II. The 3EPLL-III is based on processing the individual phase abc signals. This approach has the advantage of making variables of individual phases available. The variables of symmetrical components need to be calculated subsequently. The chapter presents details of this PLL. The structural block diagram of the 3EPLL-III comprises three similar core units, used for three phases of the input signal, and a frequency estimation (FE) block that is shared by all three cores. The 3EPLL-III directly estimates the amplitudes and phase angles of the abc signals and also the system's frequency. The chapter provides two different methods for the positive sequence component. It discusses the mathematical derivation of 3EPLL-III and provides design guidelines of 3EPLL-III . View full abstract»

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      REFERENCES

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      Index

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      IEEE Press Series on Microelectronic Systems

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