Optimizing locality in graph computations using reuse distance profiles

This work tries to answer the question of whether or not we should write code differently when the underlying chip microarchitecture is powered by a multicore processor. We use a set of three graph benchmarks each with three different input problems varying in size and connectivity to characterize the importance of how we partition the problem space among cores and how that partitioning can happen at multiple levels of the cache leading to better performance. We explore a design space represented by different parallelization schemes and different graph partitionings. This provides a large and complex space that we characterize using detailed simulation results to see how much gain we can obtain over a baseline legacy parallelization technique with a partition sized to fit in the L1 cache. We show that the legacy parallelization is not the best alternative in most of the cases and other parallelization techniques perform better. We use a PIN computed reuse distance profile to build an execution time prediction model that rank orders the different combinations of parallelization strategies and partitioning sizes. In some cases the prediction is 100% accurate and in some other cases the prediction projects worse performance than the baseline case. We report the difference between the simulated best performing combination and the PIN predicted ones. The M5 performance simulations show gains of up to 20% relative to the baseline. Our prediction scheme can achieve up to 100% of the best performance gains obtained by M5 and up to 48% on average across all of our benchmarks and input sizes. We have shown a new application for reuse distance profiles-i.e., as a tool for helping program developers and compilers to optimize program performance.