Implementation of 40 Mbps burst QPSK receiver with NDA timing and frequency synchronization

This paper presents a case of design and implementation of a high-speed burst QPSK (quaternary phase shift keying) receiver. Since the PSK modulation transmits its information within the phase, the baseband digital receiver can recover the transmitted symbol from the received phase. Symbol time and frequency offset estimators estimate symbol time and frequency offset using sample data over 32 symbols without transmitted symbol information, respectively, and internal RAM is used for the received phase delay over the estimation time. The receiver is implemented using about 92000 gates of Samsung KG75 SOG library, which uses 0.65 /spl mu/m CMOS technology. The chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.