Design of Testable Adder Circuits for Spintronics Based Nanomagnetic Computing

In this work, we have proposed an implementation of a testable reversible adder using conservative reversible logic for Spintronics based nanomagnetic logic (NML). The testable adder has the advantage that all unidirectional stuck at faults can be detected concurrently while the circuit is performing the normal operation. Further, the unidirectional faults can also be tested offline using only two test vectors, all 0's and all 1's. Two methodologies for the design of testable reversible ripple carry adder are investigated. The first method makes use of two different logic blocks that can be cascaded to form reversible ripple carry adders. The second method is a classical approach in which full adders are cascaded in ripple carry fashion. The promising finding of this work is that even though method 1 is an attractive choice to design testable reversible adders in quantum computing, for NML computing method 2 is attractive because of its improvement in propagation delay and NML cost.