3D interconnect simulation applied to CMP thickness variations

Thickness variations of ILD CMP induced yield loss at wafer edge is simulated by 3D Sentaurus Interconnect, in order to achieve more authentic condition, we adopt the image contour extraction technique to stream the genuine contact contour gds together with STI, POLY, ML database. The results demonstrates that when the thickness is over 7k at wafer edge, there is no electric current found, and it has etching stop phenomenon. After optimizing the CMP recipe according the simulation results, the yield of wafer edge get great improvement.