Design of a wideband digitally controlled oscillator

This paper presents a wide-band digitally controlled oscillator (DCO) applied in all digital phase locked loop (ADPLL) of which the tuning range is 3GHz-5.3GHz. Capacitor tank of the oscillator contains 3 major arrays: coarse tuning bank, medium tuning bank and fine tuning bank (including fractional tuning capacitors), which are all formed by varactors. Post-layout simulation is done to verify its performance on SMIC 40nm process. The oscillator phase noise is -137dBc/Hz at 3MHz, 3.7GHz, and power consumption is 8.6mW and 7mW respectively where center frequency is 3GHz and 5.3GHz.