Time-Interleaved $\Sigma\Delta$ Modulators for FPGAs

This brief describes and analyzes a technique of increasing a sampling rate in a sigma-delta (ΣΔ) modulator based on a discrete-time description, which is an extension of existing techniques of parallelization. The limitations in the signalto-noise ratio and the maximum increase of the sampling rate in a digital system are explained, and a structure of a low-pass ΣΔ modulator characterized by a short critical path is used in this brief to validate the technique. An implementation of a modulator shows the increase in the sampling rate from 100 to 400 MHz.