A 1.6GHz/4.8GHz dual-band CMOS fractional-N frequency synthesizer for S-Band radio applications

A 1.6 GHz/ 4.8 GHz fractional-N frequency synthesizer in 0.18-μm CMOS technology is presented in this paper. Its purpose is to generate the local oscillator (LO) signals for a fully integrated S-Band transceiver with a direct-conversion receiver (RX) and a dual up-conversion transmitter (TX) to avoid the frequency pulling problem. The synthesizer achieves phase noise of -141.3 dBc/Hz at 1.62 GHz and -132.6 dBc/Hz at 4.86 GHz (both at 3 MHz offset), with reference spurs <;-70.2 dBc for the lower band (LB) and <;-63.8 dBc for the higher band (HB). Total power consumption is 18.2-22.7 mW from a 1 V supply for the VCO and 1.8V for the other synthesizer blocks.