Virtual UARTs for Reconfigurable Multi-processor Architectures

This paper targets the time-consuming problem of user IOs and debugging in MPSoC. It introduces the concept of dynamic allocation of virtual UARTs to implement standard-IOs in various hardware and software contexts, on a hybrid FPGA. It discusses the advantages and limitations of this abstraction, presents an implementation on the hybrid Xilinx Zynq device. Multiple experiences illustrate how hardware (processors) and software heterogeneities can be handled. As a result, a real MJPEG decoder is debugged and validated in a couple of hours thanks to standard-IOs and virtual UARTs.