An efficient implementation of self timed audio Sigma-Delta Modulator

This paper presents Self Timed First Order Sigma-Delta Modulator for audio applications. Implementation completely avoids sampling clock and thus no clock related issues like quantization noise, jitter etc. Analog circuit complexity reduces due to self timed, input activity dependent sampling. So leads to minimum power consumption. Overall it provides asynchronous sampling. Compared to synchronous counterpart the quantizer provides variable resolution and less power consumption. The proposed design shows Asynchronous Sigma-Delta Modulator (ASDM) with tuning of hysteresis level externally. Probably this is the first ASDM scheme which uses Schmitt Trigger with tunable hysteresis. Depending on input signal speed we can externally set the resolution, without corrupting inband spectrum. Performance is improved by implementation with effective switching rate. It enables the control on dynamic power consumption. Design implemented in UMC CMOS technology for ±1.2V using Cadence Design System for 5KHz-20KHz signal frequency range. Extensive simulations show that with Over Cycling Ratio (OCR) 100, modulator achieves maximum SNDR 110dB, SFDR 76dB with power dissipation 153μW.