On the improved implementations of pre calculated sums of partial products based 7-bit unsigned parallel squarer

In [1,2], K-J Cho et al proposed a 7-bit unsigned high performance parallel squarer design, using pre-calculated sums of partial products. This paper presents two improved implementations of this technique. The first implementation is based upon optimized interconnections between generation and reduction stages of the squarer. The second implementation is built using a hierarchical carry look-ahead adder (CLA) (with different block sizes per level) and optimized interconnections of the first implementation. Analytical evaluation is done with respect to the nominal delay model, total fan-in, and a gate delay model that accounts for fan-in and fan-out dependencies. The analytical results indicate that the first implementation speeds up squaring operations at no additional cost. In contrast, the second implementation is efficient in terms of area and power savings but the price paid is 5.53% reduction in speed relative to the precalculated sums based squarer.