Investigation of area and speed trade-offs in FPGA implementation of an image correlation algorithm

In this paper an image correlation algorithm is implemented on FPGA architecture for assisted movements of visually impaired persons or automotive driving systems. Taking into account the limitations of FPGA devices and the special requirements of the correlation based image matching algorithm a semi-parallel approach is proposed. This provides an optimal tradeoff between area and speed of the implemented algorithm. Several key issues are investigated and discussed related to the speed and area.