An asynchronous mixed-mode neuro-fuzzy controller for energy efficient machine intelligence SoC

This paper presents an asynchronous digital-analog mixed-mode neuro-fuzzy controller that enables energy efficient implementation of machine intelligence SoC. The proposed neuro-fuzzy controller adopts an asynchronous 2-stage pipeline for analog and digital domain operations, which is the main contributor to high throughput and energy efficient machine intelligence SoC. To this end, a neuro-fuzzy controller with a delay prediction unit and a new ISA is introduced to modify the stage depth of mixed-mode pipeline incorporating with highly parallel special function units. Compared to the conventional digital standalone VLSI architecture, power reduction and processing speed acceleration are achieved by 46.6% and 71.4%, respectively, reporting 12.5μJ/epoch energy efficiency.