Comparative Study on Energy-Efficiencies of Single-Electron Transistor-Based Binary Full Adders Including Nonideal Effects

Performances and energy efficiencies of various single-electron transistor-based (SET-based) binary full adders (FAs) are comparatively investigated with optimization of device parameters by means of simulation program with integrated circuit emphasis models including nonideal effects commonly observed in really implemented SETs. The proposed binary decision diagram (BDD) cell-based 1-bit FA is the most promising in terms of energy efficiency (τ=0.3 aJ/state), power dissipation (P = 1.2 nW), delay (τ=20 ps), and immunity to process variations (background charge noise ΔQ
₀
<; ±0.112q and control gate capacitance mismatch ΔC
_cg
<; 0.5 × C
_cg
) at the expense of hardware burden, compared with majority gate-based SET FAs (3.988 aJ/state, P = 15.95nW, τ=52 ps, ΔQ
₀
<; ±0.0392q, ΔC
_cg
<; 0.35 × C
_cg
) and SET threshold logic gate-based FAs (3.845 aJ/state, P=15.38nW, τ=107 ps, ΔQ
₀
<; ±0.028q, ΔC
_cg
<; 0.2 × C
_cg
). It is also found that the SET itself dominates the power dissipation in SET-based FAs and the static dc power plays a significant role in power consumption in SET-based FAs, compared with the dynamic power, regardless of the FA type. In addition, SET-based BDD FAs are compared with their CMOS counterparts.