SysPy: using Python for processor-centric SoC design

Although software engineers have high performance algorithms that could be implemented power-efficiently as embedded Systems on Chip (SoC) with modern FPGAs, there is still no easy path for them to a hardware realization, mainly due to the lack of appropriate design tools. We present an overview of a tool we have developed to boost the productivity of processor-centric SoC designs for FPGAs. Our tool called SysPy (System Python) exploits the strengths of the popular Python scripting language and acts as a “glue software” between mature HDLs, ready-to-use VHDL components and programmable processor soft IP cores. SysPy can be used to: (i) describe hardware components in Python that the tool will automatically translate to correct high quality VHDL, (ii) build top-level structural descriptions of SoCs based on components that are defined in Python, VHDL or pre-synthesized netlist files, (iii) implement without any user effort all the steps needed to take the user's C code for a programmable processor soft IP core and automatically produce a synthesizable VHDL description for the targeted Xilinx FPGA device. The top-level SoC description is in Python, facilitating Hw/Sw re-partitioning and efficient iterative design for SoC performance tuning.